Sr. Manager Engineering

WHAT YOU DO AT AMD CHANGES EVERYTHING

We care deeply about transforming lives with AMD technology to enrich our industry, our communities, and the world. Our mission is to build great products that accelerate next-generation computing experiences the building blocks for the data center, artificial intelligence, PCs, gaming and embedded. Underpinning our mission is the AMD culture. We push the limits of innovation to solve the world s most important challenges. We strive for execution excellence while being direct, humble, collaborative, and inclusive of diverse perspectives.

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We are seeking an experienced RTL Design Leader/Manager with strong technical and leadership skills, who thrives in a fast-paced environment, to lead a talented team of engineers. It is a challenging position that involves working at a fast pace & agility to meet Quality & schedule for the IP delivery. Come join the AMD team!

THE ROLE :

We are looking for a Senior Manager RTL Design to lead a team of talented engineers in developing next generation IPU IP/AI silicon. This IP goes to several products including client products & serve as ML inference accelerator.

This role will require deep understanding of design implementation and flows, tools and methodologies , including power intent UPF specifications. This role requries 15+ years of experience in logic design & 5+ years of experience managing teams.

THE PERSON :

Successful candidate will have an ASIC Design background/education, would have participated in silicon design projects as Technical lead/Manager and has a history of achieving quality deliverables meeting schedule in fast pace, Innovation & stakeholder interaction. Basic knowledge of ML, power-performance-Area optimizations, low power designs preferred.

KEY RESPONISIBILITES :

• Manage Logic design team for IPU / AI Engine building blocks and necessary infrastructure based on architecture, PPA, DFX, Functional Safety requirement etc. . .
• Drive the design execution using technical expertise, mentoring team of engineers & being responsbile for overall execution Quality & schedule. Define and implement RTL design methodologies and best practices. Lead team, meet schedule commitments and provide strong support to various customers.
• Ensure Design meets performance, power and Area targets & good verificaiton coverage for zero bugs in silicon.
• RTL design and debug of relevant blocks to realize the low power architecture in silicon.
• Work with verification and physical design teams to achieve high quality design and successful tape out
• Contribute in cross-functional teams to solve novel problems across multiple functional areas in development of required features and/or algorithms
• Collaborate with cross-functional teams to solve novel problems across multiple functional areas.
• Perform RTL-Level design verfication and debugging as needed.

PREFERRED EXPERIENCES :

• Atleast 5+ years of experience managing design teams.
• 15+ years of Strong design expertise in ASIC designs, RTL design in Verilog/System Verilog, preferably in complex IP like CPU/GPU etc. .
• Modern SOC tools such as Spyglass, Questa CDC, Cadence Conformal Low Power, VCS simulation
• Expertise in Low power digital design and analysis. Low Power Design Experience for power domains and power islands using UPF flows and Cadence Conformal Low Power.
• Expertise in circuit timing/STA, and practical experience with Prime Time or equivalent tools
• Good Understanding of Machine learning concepts.
• hands-on with TCL, Perl, Python scripting,
• Strong verbal and written communication skills
• Ability to organize and present complex technical information

ACADEMIC CREDENTIALS:

• Bachelors or Masters degree in computer engineering/Electrical Engineering