Staff Engineer Design

Experience in working on full-chip STA closure, defining mode requirements and corners for timing closure

In your new role you will:

• Develop and implement high-performance, low-power, and area-efficient digital designs for SoCs using industry-standard EDA tools.
• Work closely with design teams to understand requirements and constraints of the design, and provide feedback on design feasibility, timing and power.
• Debug and resolve design issues related to synthesis, timing, power and area.
• Understanding of DFT flows, including scan insertion and ATPG .
• Experience in working on full-chip STA closure , defining mode requirements and corners for timing closure.
• Experience with Timing ECO techniques and implementation.
• Perform power analysis and optimize designs for low power.
• Proficient with EDA tools from Synopsys\/Cadence\/Mentor.
• Excellent analytical & communication skills.
• Shown ability to collaborate in a multi-functional environment, cross-site or cross-time zone.
• Proficient in Tcl and Perl or other scripting relevant language is a plus.

You are best equipped for this task if you have:

• Bachelors or Masters in Electrical\/Electronics Engineering with 5+ years of relevant experience.
• Strong understanding of digital design principles.
• In-depth knowledge of synthesis & Timing methodologies and tools from leading EDA vendors.
• Experience with power analysis and optimization flows such as power gating, clock gating , voltage scaling, and dynamic
• voltage frequency scaling.
• Excellent problem-solving skills and ability to work independently and in a team environment.
• Strong communication and interpersonal skills, with the ability to interact effectively with cross-functional teams.
• Proven track record of delivering successful designs on time, meeting performance, power, and area goals.