Staff SOC Engineer

• Contribute to highly complex designs in a multi-site organization covering all aspects of Structural and Physical SoC Design
• Be responsible for the physical design of multifarious digital SoCs
• Translate requirements into layout specifics using our state-of-the-art EDA tools and flows
• Work independently in different phases of the RTL2GDS flow : With focus on (one or many) Synthesis and equivalence check, generation of Floorplans, Placement, Clock Trees, Routing and Power Distribution Network for efficient Timing Closure with Signal Integrity and Physical Sign off including Power Integrity
• Take physical limitation of hierarchical deep sub-micron designs into account and timely implement suitable solutions to overcome implementation issues.
• Tap your experience to contribute significantly to the development and implementation of clocking architectures
• Be a member of an expert network and participate to drive innovation, methodology and flow topics in the SoC Floorplanning and Top-Level Timing Closure domain for next generation SoCs

You are best equipped for this task if you have:

• A degree in Electrical Engineering, Microelectronics or a similar field
• At least 5 years of working experience in Physical Design handling highly complex SoCs - with sound experience in Synthesis, Place & Route and Timing Closure and involvement in FINFET technologies
• Know-how in technical leadership in physical design projects
• Sound programming skills and knowledge in scripting languages like Tcl, Perl or Python
• Basic experience in RTL coding
• Understanding of Functional Safety will be a benefit
• Fluent English language skills \u2013 with German being an added plus