Mixed Signal IP Verification Engineer

locationsIndia, Bangalore

time typeFull time

posted onPosted 10 Days Ago

job requisition idJR0272667



Job Details:

About The Role :

The Memory IP Group (MIP) within the Client Computing Group (CCG) is looking for a Pre-Silicon Verification Engineer to deliver latest and best-in-class DDR PHY IP for SoCs across Intel for the latest desktop, laptop, and other products.

In this role you will perform all aspects of the functional verification flow to ensure design will meet specification requirements.

You will perform IP Verification related tasks such as creating test plan, defining TB architecture and creating test benches, validating design and micro-architectural implementation.

You will be automating validation tasks to drive efficiency.You will be analyzing results and help to debug issues in pre-silicon environment at IP, subsystem and SOC level.You will collaborate with digital and analog architects, RTL developers, and physical design teams to improve verification of complex architectural and microarchitectural features and to meet functional, performance, and power goals.

The additional responsibilities includedevelopment of validation strategies and plans, scoping and driving execution for different area of pre-Si validation, driving technical reviews of plans and proofs with design and architecture teams, maintaining and improving existing functional verification infrastructure and methodology, providing guidance and help to team members in understanding issues, removing roadblocks and ensuring issue resolution through strong demonstration of Intel Cultural values.

Qualifications:

Candidate must possess a BS, MS degree with 10-15 years of relevant industry experience in Design verification, System Verilog and OVM/UVM.

Candidate must be experienced in validation flow right from test plan creation to verification closure, waveform debug, functional coverage, code coverage, VCS NLP and non-NLP simulations and GLS

Capable of multitasking in dynamic environment with multiple teams from different geos

Solid verbal and written communication skills

Excellent debug and problem solving skills

Preferred Qualifications:

Knowledge of DDRPHY validation with good hold on DFI/DDR/LPDDR protocols

Good scripting skills in Python/Perl

Exposed to Formal Property Verification and Git/Perforce/CVS version control

Job Type: Experienced Hire

Shift: Shift 1 (India)

Primary Location: India, Bangalore

Additional Locations:

Business group: The Client Computing Group (CCG) is responsible for driving business strategy and product development for Intel's PC products and platforms, spanning form factors such as notebooks, desktops, 2 in 1s, all in ones. Working with our partners across the industry, we intend to deliver purposeful computing experiences that unlock people's potential - allowing each person use our products to focus, create and connect in ways that matter most to them. As the largest business unit at Intel, CCG is investing more heavily in the PC, ramping its capabilities even more aggressively, and designing the PC experience even more deliberately, including delivering a predictable cadence of leadership products. As a result, we are able to fuel innovation across Intel, providing an important source of IP and scale, as well as help the company deliver on its purpose of enriching the lives of every person on earth.

Posting Statement: All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.

Position of Trust N/A

Work Model for this Role
This role will be eligible for our hybrid work model which allows employees to split their time between working on-site at their assigned Intel site and off-site. *