Applications Engineering, Staff Engineer

As a Logic Library Applications engineer, you will be part of a team of engineers that use place and route & other techniques to demonstrate the competitiveness of Synopsys DesignWare Logic Libraries to potential customers. This is a great position for an engineer that is competitive and loves a challenge. You will learn how to optimize design PPA through logic library cell selection and place and route methodologies, using tools such as Synopsys Fusion Compiler and PrimeTime. You will work with the most advanced semiconductor technology nodes from all the major foundries in the world on many designs with different PPA tradeoffs and present your results to customers to show them why they should purchase our products.

Your responsibilities will include:

Requirements

• Qualified applicants will have a BSEE, MSEE preferred, and 8+ years of design implementation experience. Good understanding of design methodologies is required, with emphasis placed on the backend physical design process. Knowledge of the front-end design process or experience with Place and Route, Timing signoff, Synthesis, Extraction, and LVS/DRC are a plus.
• Synopsys tool experience is desired, but not required. Excellent verbal and written presentation and communication skills are required. Customer sensitivity, the ability to multiplex many issues and have a helpful/caring attitude towards customers.
• Prior experience in customer facing role is preferred. Good written and verbal communication skills and problem solving skills are required.