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13 GreenWave Radios Jobs
Senior Engineer, Design Verification
GreenWave Radios
posted 3+ weeks ago
Job Description
- Develop testbench environment to perform verification of the design at IP/ Subsystem and SoC Level using SystemVerilog and UVM.
- Construct SoC level testbench re-using verification components developed at the IP/ Subsystem level. Test bench architecture for random/directed testing, stimulus generation, and integration of custom and off the shelf VIP/UVCs.
- Develop and execute verification plans based on design specifications and collaboration with architects and designers.
- Construct HW/SW Co-Verification environment - test-benches, use-cases, APIs, sequences. Execute and Debug use-cases.
- Be part of a dynamic and functionally diverse team with opportunities for gaining exposure to modelling (TLM), HW emulation/acceleration, and SW driven verification.
- Debug test cases and report verification result to achieve expected code/functional coverage metrics. Utilize constrained random verification, functional coverage, code coverage and assertions to achieve goals.
- Assist in emulation, FPGA, prototyping efforts.
- Implement and maintain automated verification flows in languages such as Python, Perl/ Shell scripts.
- Masters and/or bachelor s degree in engineering (or equivalent) in EC/ EE/ CS
- 5 or more years of experience in design verification with proven experience in full chip verification from test plan development to tape-out sign-off
- Good understanding of the complete verification life cycle (test plan, testbench through coverage closure)
- Expertise in developing testbench environment and verification components (Monitor, Scoreboard, Driver, Agent etc.) from the scratch
- Proficient in System Verilog, Verilog/VHDL, UVM and C; and scripting languages like Python, Perl and Tcl/Shell
- Experience in developing IP/ Subsystem/ chip-level System Verilog and UVM based test bench environments, writing System Verilog Assertions (SVAs), with embedded software design and testing
- Strong knowledge about multiple testbench architectures, industry-standard interfaces/ protocols (AXI, AHB, APB etc.)
- Experience in Cadence Design Tools/ Environments and exposure to Cadence VIPs/ UVCs is plus
- Track record of successfully executing block or chip-level verification plans
- Excellent communication and presentation skills, energetic and self-motivated
- Work effectively with an off-site/ offshore design and verification teams across locations
Employment Type: Full Time, Permanent
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