Physical Design Technical Manager

M.E./M.Tech in Electronics/Electrical Engineering with minimum of 10 years of strong, hands on Physical Design experience. Must have handled Netlist to GDS II at Top level or Hierarchical top level for at least 5 tape outs. Must have lead physical design team with hands on exposure in most of the following depending up on senior level or lead level role. Should have experience in 28nm below technologies (preferably 20nm below). Top level die size estimation, floor-planning, power estimation, power planning. IO Planning and package compatibility sign off. ESD analysis on IO ring and sign off. Netlist and constraint sign in checks and validation. Design implementation environment setup. Static and Dynamic power analysis at the top level. Netlist to GDS II implementation at chip level Hierarchical chip planning, block planning, block level constraint development, hierarchical clock tree implementation, block integration and chip finishing. Multimode multi corner optimization and closure at top level. Clock tree synthesis and advanced clock tree implementation at full chip level. Top level timing closure with sign off STA in MMMC with cross-talk and OCV. Top level ECO implementation strategy development for netlist, RTL and timing level changes Methodology development, customization as per the specific design need. Good hands-on knowledge in reference flows, excellent debugging skills. Scripting experience in Perl/TCL. Flow customization and fine tuning for Power, Performance, Area. Technical leadership and ability to mentor and make the team deliver. Strong inter-personal skills and ability to work with multiple teams. In depth exposure in Implementation in any of the following platforms. FC/ICC/Innovus; Tool exposure in Sign Off DRC/LVS : Calibre Timing sign off : Primetime PNA : Apache -Redhawk Job Type: Full-time Experience: Physical Design: 10-15 years Should have worked as technical lead for at least 2 projects. M.E./M.Tech in Electronics/Electrical Engineering with minimum of 10 years of strong, hands on Physical Design experience. Must have handled Netlist to GDS II at Top level or Hierarchical top level for at least 5 tape outs. Must have lead physical design team with hands on exposure in most of the following depending up on senior level or lead level role. Should have experience in 28nm below technologies (preferably 20nm below). Top level die size estimation, floor-planning, power estimation, power planning. IO Planning and package compatibility sign off. ESD analysis on IO ring and sign off. Netlist and constraint sign in checks and validation. Design implementation environment setup. Static and Dynamic power analysis at the top level. Netlist to GDS II implementation at chip level Hierarchical chip planning, block planning, block level constraint development, hierarchical clock tree implementation, block integration and chip finishing. Multimode multi corner optimization and closure at top level. Clock tree synthesis and advanced clock tree implementation at full chip level. Top level timing closure with sign off STA in MMMC with cross-talk and OCV. Top level ECO implementation strategy development for netlist, RTL and timing level changes Methodology development, customization as per the specific design need. Good hands-on knowledge in reference flows, excellent debugging skills. Scripting experience in Perl/TCL. Flow customization and fine tuning for Power, Performance, Area. Technical leadership and ability to mentor and make the team deliver. Strong inter-personal skills and ability to work with multiple teams. In depth exposure in Implementation in any of the following platforms. FC/ICC/Innovus; Tool exposure in Sign Off DRC/LVS : Calibre Timing sign off : Primetime PNA : Apache -Redhawk Job Type: Full-time Experience: Physical Design: 10-15 years Should have worked as technical lead for at least 2 projects.