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VMware Software

Compare

4.4

based on 1.1k Reviews

Video summary

1 VMware Software Senior Engineer Job

Senior Engineer - Memory Design Validation

VMware India

4.4

based on 1.1k Reviews

6-10 years

Bangalore / Bengaluru

1 vacancy

Senior Engineer - Memory Design Validation

VMware Software

posted 3 weeks ago

Job Role Insights

Flexible timing

Key skills for the job

Data Analysis Python Automation Testing Perl Silicon Validation DFT

+ 3 more

Job Description

Job Description:

Contribute/Lead towards Memory Design Validation of SRAM, Multi-Ports, Register File, TCAM, and ROM memory compilers as well as custom macros in 2nm and other cutting edge process technologies

Job Description

Contribute/Lead towards Memory Design Validation of all types of custom memory macros and memory compilers
Perform functional verification, root cause design discrepancies, and help resolve them
Perform signal integrity analysis, identify design weaknesses, and propose possible solutions to address them
Perform transistor level simulations to check for any Power Up or Lock up issues and help resolve them
Perform EM/IR analysis/simulations and evaluate impact on timing and internal margins
Perform transistor level simulations to validate timing and internal margins, identify timing characterization holes, and help resolve them
Perform various QA and validation checks to ensure accurate timing and power models
Develop scripts to automate verification flow and data analysis
Support silicon debugs and correlation to spice models
Coordinate with memory design leads, modelling leads, and managers to define and execute on the memory validation plan

Skill Sets

Strong expertise in development of memory macros of all types and architectures
Strong understanding of transistor level circuit behavior and analysis
Good understanding of the layout and their related challenges in sub nanometer process technologies
Good understanding of signal integrity, EM/IR, and reliability analysis
Good understanding of memory behavioral and physical models
Good understanding of DFT Schemes and chip level integration
Proficient in running transistor level simulators, writing automation scripts, and are tools savvy
Complete hands on experience in using Cadence schematic/layout editor tools
Complete hands on experience with transistor level simulators, Monte Carlo variation analysis, waveform viewer tools such as; HSPICE, HSIM, XA, FineSim, XARA, nWave, waveform viewer, etc..
Experience in Skill/Perl/Python Scripting is a strong plus
Good communication, interpersonal, and leadership skills
Good debugging skills, problem solving and logical reasoning skills
Motivated, self-driven and good at multi-tasking