Asic Verification Engineer

🔍 Hiring Now: Design Verification Engineers (Multiple Openings)

📍 Locations: Bangalore & Pune
🧠 Experience: 4+ to 18 Years
📅 Notice Period: Immediate to 30 Days
📧 Email: prabhu.p@acldigital.com
📱 WhatsApp: 8754387484

✅ Current Openings

1️⃣ Senior Design Verification Engineer 10+ Years (Bangalore) – 1 Position

• Strong expertise in SystemVerilog (SV) and UVM-based verification
  
• Mandatory: Experience with ARM Coresight Debug subsystem
  
• Strong debugging and problem-solving skills
  

2️⃣ Design Verification Engineer – 5+ Years (Bangalore) – 2 Positions

• Proficient in SystemVerilog (SV) and UVM
  
• Preferred: ARM Coresight Debug subsystem knowledge
  
• Strong debugging expertise required
  

3️⃣ Design Verification Engineer – 8+ Years (Bangalore) – 2 Positions

• Solid experience with SV and UVM
  
• Mandatory: CSI/DSI Protocol knowledge
  
• Excellent debugging capabilities
  

4️⃣ Design Verification Engineer – 8+ Years (Pune Preferred / Bangalore) – 2 Positions

• Expertise in SystemVerilog (SV) and UVM
  
• Mandatory: Experience with Memory Controller or Cache
  
• Strong debug experience is essential
  

💼 Why Join ACL Digital?

• Work on cutting-edge SoC & IP designs with global semiconductor leaders
  
• Opportunity to contribute across leading technology nodes
  
• Fast-paced, innovation-driven culture with career growth opportunities
  

📩 Interested candidates can apply now by sharing their CV to prabhu.p@acldigital.com or WhatsApp 8754387484.