Cadence Design Systems - DFT Engineer - Embedded System (10-14 yrs)

About the Role :

We are seeking highly skilled and motivated DFT Engineers to join our dynamic semiconductor design team. The ideal candidate will have extensive experience in SCAN/ATPG/JTAG/MBIST implementation and verification, along with hands-on involvement in multiple chip tape-outs and post-silicon bring-up on ATE platforms. You will be an integral part of the silicon development lifecycle, contributing to DFT architecture, verification, and debug.

Key Responsibilities :

- Develop and implement SCAN, ATPG, JTAG, and MBIST architectures at block and top level.

- Execute scan insertion and DFT rule checking at RTL/Netlist level.

- Work on Memory BIST generation, insertion, and functional verification.

- Perform gate-level simulations (GLS) with and without timing (SDF).

- Develop and integrate test structures for DFT, including IP integration, fault modeling, test

point insertion, and coverage optimization.

- Collaborate with cross-functional teams (Design, Synthesis, STA, and PD) to resolve DFT

integration issues.

- Work on IEEE standard JTAG architectures (1149.1 / 1149.6) and related scan chain verification.

- Define and validate test mode timing constraints and participate in STA signoff.

- Support silicon bring-up and debugging on ATE platforms, ensuring high-quality silicon validation.

- Utilize industry-standard tools (Cadence, Synopsys, Siemens Tessent) for ATPG, MBIST, and boundary scan implementation.

- Create and maintain DFT scripts using Perl, Tcl, or similar scripting languages.

Required Skills & Qualifications :

- Bachelor's or Master's degree in Electronics, Electrical, or related Engineering fields.

- 10 - 14 years of relevant experience in DFT implementation and validation.

- Strong understanding of digital design principles, scan logic, and fault models.

- Hands-on experience with scan/ATPG tools (preferably Tessent or Cadence).

- Proficient in GLS with and without timing (SDF).

- Knowledge of Analog PHY/Macro test concepts and integration.

- Solid understanding of JTAG and IEEE standards (1149.x).

- Proficiency in Perl/Tcl scripting for automation of DFT flows.

- Proven experience in resolving DFT issues through collaboration with multi-disciplinary

teams.

- Strong verbal and written communication skills.

- Ability to take ownership and work independently in a fast-paced environment.

Preferred :

- Experience with multiple successful chip tape-outs and post-silicon validation.

- Familiarity with STA and timing closure for test modes.