Tecquire Solutions - RTL Engineer - System Verilog (5-8 yrs)

Job Summary :

We are looking for an experienced Senior RTL Design Engineer with a strong background in SoC architecture, logic design, and RTL development. This role is ideal for candidates who are passionate about software-driven digital hardware design and have in-depth knowledge of modern SoC systems, protocols, and low-power design techniques.

Key Responsibilities :

- Design and implement scalable RTL architectures for complex SoC components using Verilog/SystemVerilog.

- Develop and maintain logic blocks aligned with architectural and functional specifications.

- Collaborate with design verification and architecture teams to define module interfaces and performance metrics.

- Implement low-power design techniques using software methodologies such as clock gating, power domain partitioning, etc.

- Model asynchronous interfaces and multi-clock domain logic for integration into larger SoC platforms.

- Analyze design performance and optimize RTL for area, power, and logical efficiency.

- Write clean, reusable, and synthesis-friendly RTL code following best practices and coding standards.

- Simulate and debug logic design using industry tools and waveform analysis.

- Integrate IPs and subsystems in a modular and maintainable way using software configuration and scripting techniques.

Required Skills & Experience :

- 5+ years of experience in RTL design, logic development, and micro-architecture.

- Strong command over Verilog/SystemVerilog and digital design methodologies.

- Proven experience in designing software-driven SoC architectures with modular, configurable

RTL.

- In-depth knowledge of AMBA protocols - AXI, AHB, APB.

- Experience in multi-clock domain logic and asynchronous interface design.

- Proficiency in low-power RTL techniques including power-aware coding and UPF/CPF flows (logic-level).

- Familiarity with RTL design tools such as Simulation (ModelSim/VCS), Linting, CDC/RDC tools.

- Scripting skills in TCL, Python, or Shell for automating RTL testbenches, configuration, or IP integration.

Preferred Qualifications :

- Bachelors or Masters degree in, Computer Engineering, or related field.

- Exposure to software-based SoC modeling or transaction-level modeling (TLM).

- Experience with design abstraction, reusable IP architecture, and configurable RTL

components.

- Knowledge of interfaces such as USB, PCIe, SD/eMMC at RTL level.