Western Digital - Principal Engineer - ASIC/RTL Design (7-10 yrs)

Responsibilities :

- Lead and contribute to the micro-architecture and RTL implementation of complex digital blocks for large SoCs using Verilog/SystemVerilog.

- Demonstrate expertise in handling complex designs with multiple clock domains and ensuring proper synchronization and

functionality.

- Possess strong knowledge and experience with various bus matrix architectures, including AHB, AXI, and Network-on-Chip (NOC) designs.

- Utilize your understanding of low power design methodologies to implement power-efficient RTL.

- Expertly handle Clock Domain Crossing (CDC) designs, ensuring data integrity and functional correctness across asynchronous interfaces.

- Drive and participate in static verification using Spyglass Lint and CDC tools, performing thorough report analysis and achieving design signoff.

- (Plus) Contribute to Synthesis using Synopsys Design Compiler (DC), performing timing analysis, and working towards timing closure.

- (Plus) Leverage your scripting skills in Perl, Python, and TCL to automate design and verification flows.

- Demonstrate the ability to quickly ramp up on new architectures and technologies.

- Work cohesively and effectively with Verification and Validation teams to ensure robust and high-quality designs.

- Maintain a positive and proactive attitude, demonstrating a solution-oriented approach to challenges.

- Possess excellent written and verbal communication skills to effectively collaborate with local and remote teams.

Qualifications :

Minimum Qualifications :

- Bachelor's degree with 7+ years of experience, OR

- Master's degree with 6+ years of experience in a related field.

- Minimum of 7 years of hands-on experience in ASIC/IP Digital Design for large System-on-Chips (SoCs).

- Expertise in the implementation of RTL (Register Transfer Level) in Verilog and SystemVerilog for complex digital designs.

- Expertise in managing and implementing designs with multiple clock domains.

- Expertise with various bus matrix architectures, including AHB, AXI, and NOC designs.

- Solid understanding and experience in low power design methodologies.

- Proven experience in handling and resolving Clock Domain Crossing (CDC) issues in complex designs.

- Hands-on experience with Spyglass Lint and CDC checks, including report analysis and achieving design signoff.

Preferred Qualifications (Plus) :

- Experience with ARM processor subsystems and/or NAND Flash memory subsystems.

- Experience in Synthesis using Synopsys Design Compiler (DC) and performing timing analysis and closure.

- Proficiency in scripting languages such as Perl, Python, and TCL for automation.