Filter interviews by
I applied via Company Website and was interviewed in Jan 2024. There were 3 interview rounds.
You have to cut a cake maximum 3 times which should make 8 equal halves
My strong background in design and verification, along with my problem-solving skills and attention to detail, make me a great fit for this role.
Extensive experience in design and verification methodologies
Proven track record of successfully completing complex projects
Strong problem-solving skills and attention to detail
Ability to work well in a team environment
Familiarity with industry-standard tools and technologies
Top trending discussions
posted on 16 Aug 2023
I applied via Naukri.com and was interviewed in Jul 2023. There were 2 interview rounds.
posted on 2 Oct 2024
I applied via Campus Placement and was interviewed in Sep 2024. There were 2 interview rounds.
Basic aptitude-10 question,digital moderate -Question,analog moderate -10 question,verilog and system verilog -10 question
posted on 11 Oct 2023
I applied via Campus Placement and was interviewed before Oct 2022. There were 2 interview rounds.
A combination of Technical and Numerical aptitude. Questions on digital design, edc, vlsi.
posted on 2 Dec 2024
Aptitude+digital electronics+vhdl
posted on 31 Dec 2024
I appeared for an interview in Dec 2024.
SystemVerilog (SV) and UVM are essential for designing and verifying complex digital systems.
SystemVerilog enhances Verilog with object-oriented programming features.
UVM (Universal Verification Methodology) provides a standardized framework for verification.
Example: Using UVM, you can create reusable testbenches for different designs.
SV supports assertions, which help in checking design properties during simulation.
Exa...
SystemVerilog (SV) and UVM are essential for designing and verifying complex digital systems.
SystemVerilog is an extension of Verilog, adding features like classes, interfaces, and assertions.
UVM (Universal Verification Methodology) is a standardized methodology for verification using SystemVerilog.
UVM provides a base class library for creating reusable verification components, such as agents and testbenches.
Example: A...
posted on 27 Sep 2022
I applied via Company Website and was interviewed in Mar 2022. There were 3 interview rounds.
Had basic aptitude questions, verilog , c programming, digital electronics, analog electronics,computer architecture.
I applied via Recruitment Consulltant and was interviewed before Aug 2021. There was 1 interview round.
Stackup is decided based on the number of layers, signal integrity requirements, and manufacturing constraints.
Consider the number of layers required for the design
Evaluate signal integrity requirements and impedance control
Take into account manufacturing constraints such as minimum trace width and spacing
Balance cost and performance
Use simulation tools to optimize the stackup
Consult with PCB fabricators for their reco...
based on 1 interview experience
Difficulty level
Duration
based on 1 review
Rating in categories
Verification Engineer
63
salaries
| ₹39.7 L/yr - ₹72 L/yr |
Senior Engineer
42
salaries
| ₹23 L/yr - ₹40 L/yr |
Software Engineer
35
salaries
| ₹11.3 L/yr - ₹19.2 L/yr |
Senior Verification & Validation Engineer
33
salaries
| ₹39 L/yr - ₹72.9 L/yr |
Design Engineer
27
salaries
| ₹16.6 L/yr - ₹30.5 L/yr |
Apar Industries
Molex
TDK India Private Limited
Applied Materials