Lekha Wireless Solutions Fpga Design Engineer Interview Questions and Answers

1. Write a verilog code for SDPRAM

Q1. What is CDC and explain the CDC techniques
Ans. 
CDC stands for Clock Domain Crossing. It refers to transferring data between different clock domains in an FPGA design.
• CDC occurs when signals cross between different clock domains in an FPGA design

• CDC can lead to metastability issues if not handled properly

• Common CDC techniques include synchronizers, handshake protocols, and FIFO buffers

• Examples of CDC techniques include 2-flop synchronizers, Gray coding, and CDC FIFO...read more
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Q2. Determine the unkonw clock frequency with know one
Ans. 
Use a frequency counter or oscilloscope to measure the period of a known signal and calculate the frequency.
• Measure the period of a known signal using a frequency counter or oscilloscope.

• Calculate the frequency using the formula: Frequency = 1 / Period.

• For example, if the period of the signal is 10 ms, the frequency would be 1 / 0.01 = 100 Hz.
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Q1. Tell me about yourself
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Q2. Package discussion
Ans. 
FPGA package discussion involves understanding the physical and electrical characteristics of FPGA packages.
• Package types include BGA (Ball Grid Array) and QFN (Quad Flat No-lead).

• Thermal performance is critical; consider thermal resistance and dissipation.

• Pin count and arrangement affect routing and design complexity.

• Mechanical stress can impact reliability; choose packages that suit your application.

• Examples of FPGA ...read more
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