Layout Designer-Memory

This role does design and layout of complex VLSI (very large scale integration) circuits using graphic editing tools in cutting edge technological nodes. A major portion of the job is in creation of new physical design data from concepts, partial schematics or a working knowledge of overall requirements. Responsibilities include checking the design integrity with respect to semiconductor ground rules and the logical function of the circuit. Symbolic circuit data (schematics) are converted to physical shapes which represent the semiconductor process. The role ranges from manual shapes and checking tool manipulations to extended team coordination and methodology creation. The employee guides functional objectives or technologies.


Required education
Bachelor's Degree

Preferred education
Master's Degree

Required technical and professional expertise

5-7 Years of relevant experience in Memory Layout design for blocks like Caches, CAMs, Register files, multiport register Files, Compilers etc.Should be in a position to work hands on on memory IPs, help generate and curate new ideas for layout designing, innovate new ways of layout designing, bring leadership into work and have growth mindset and have openmindedness to automation ideas;
Excellent communication skills to be able to work with crosssite designers, EDA for development and curation of new tools needed for work.
Should be able to understand various memory architechtures, experience in bit cells layouts, compiler layout design; Should have hands on experience in Finfets, GAA etc.
Should have had experience in technology nodes below 7nm;
LVS, DRC, Antenna, DFM, EM, IR, Methodology check debugging and fixing is a must;
Leadership to drive collaborative initiatives with cross teams; SRAM designing experience is an added advantage


Preferred technical and professional experience

Scripting to ease deliverables is an added advantage. Automation skills in PERL, Python , and/or TCL