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Wafer Space Interview Questions and Answers
5 Interview questions
An 8-bit counter counts from 0 to 255 in binary, using flip-flops and logic gates for digital applications.
An 8-bit counter can represent values from 0 (00000000) to 255 (11111111).
It typically uses 8 flip-flops, each representing one bit.
Counters can be synchronous (all bits change simultaneously) or asynchronous (bits change in sequence).
Common applications include digital clocks, frequency counters, and timers.
...
FIFO depth calculation involves determining the required buffer size for data storage in digital systems.
Understand the data rate: Calculate the input and output data rates (e.g., 100 Mbps input, 50 Mbps output).
Determine the latency: Consider the maximum allowable latency for your application (e.g., 10 ms).
Calculate the FIFO depth: Use the formula FIFO Depth = (Input Rate - Output Rate) * Latency.
Example: For 100...
Converting gates using NAND gate
NAND gate can be used to implement other logic gates like AND, OR, NOT
To implement an AND gate using NAND gates, connect two NAND gates in series
To implement an OR gate using NAND gates, connect two NAND gates in parallel
To implement a NOT gate using NAND gate, connect the input directly to one input of the NAND gate and the other input to ground
CMOS stands for Complementary Metal-Oxide-Semiconductor. It is a technology used in integrated circuits for digital logic functions.
CMOS technology uses both NMOS and PMOS transistors to achieve low power consumption and high noise immunity.
In CMOS, when one transistor is on, the other is off, reducing power consumption.
CMOS circuits are widely used in microprocessors, memory chips, and other digital logic circuit...
Realisation of gates involves creating logical operations using electronic components like transistors.
Gates can be realized using various technologies such as CMOS, TTL, or RTL.
For example, an AND gate can be built using two transistors in series.
NAND gates are universal gates, meaning they can be used to create any other gate.
Realization can also be done using software simulations in tools like Logisim.
Wafer Space Interview Experiences
9 interviews found
Anonymous
I applied via Referral and was interviewed in Nov 2024. There was 1 interview round.
First was aptitude which had questions on analog, digital, network theory, microcontrollers, general aptitude question which was medium level which I clear & got one to one round. In interview he didn't ask much of interview question 1st question was on academic & design verification project, 2nd was on protocol timing diagram for which the interviewer wanted the exact print of specification sheet where my diagram was a little shabby,which made him upset & didn't continue to ask proper questions .
Interview Preparation Tips
- digital logic design
- ambha protocol
- C
I applied via LinkedIn and was interviewed in Nov 2024. There was 1 interview round.
(2 Questions)
- Q1. Counter code and waveform
- Q2. Fifo depth calculation.
- Ans.
FIFO depth calculation involves determining the required buffer size for data storage in digital systems.
Understand the data rate: Calculate the input and output data rates (e.g., 100 Mbps input, 50 Mbps output).
Determine the latency: Consider the maximum allowable latency for your application (e.g., 10 ms).
Calculate the FIFO depth: Use the formula FIFO Depth = (Input Rate - Output Rate) * Latency.
Example: For 100 Mbps...
(2 Questions)
- Q1. Cmos basic principle and working
- Q2. Conversion of gates using nand
- Ans.
Converting gates using NAND gate
NAND gate can be used to implement other logic gates like AND, OR, NOT
To implement an AND gate using NAND gates, connect two NAND gates in series
To implement an OR gate using NAND gates, connect two NAND gates in parallel
To implement a NOT gate using NAND gate, connect the input directly to one input of the NAND gate and the other input to ground
(2 Questions)
- Q1. Nmos pmos working, drain and output characteristics
- Q2. Synchronous and asynchrnous clocking
Vishnu K
I applied via Campus Placement
Normal Aptitude questions, We can prepare for it using general aptitude questions available in internet.
(1 Question)
- Q1. Technical Questions (Digital Electronics, Verilog, Computer Architecture)
(1 Question)
- Q1. HR Discussion will just our introduction and some normal hr questions
Hiregoudru Malegouda
Selected
I appeared for an interview before Jun 2024, where I was asked the following questions.
- Q1. Design 8bit counter
- Ans.
An 8-bit counter counts from 0 to 255 in binary, using flip-flops and logic gates for digital applications.
An 8-bit counter can represent values from 0 (00000000) to 255 (11111111).
It typically uses 8 flip-flops, each representing one bit.
Counters can be synchronous (all bits change simultaneously) or asynchronous (bits change in sequence).
Common applications include digital clocks, frequency counters, and timers.
Examp...
- Q2. Realisation of gates
- Ans.
Realisation of gates involves creating logical operations using electronic components like transistors.
Gates can be realized using various technologies such as CMOS, TTL, or RTL.
For example, an AND gate can be built using two transistors in series.
NAND gates are universal gates, meaning they can be used to create any other gate.
Realization can also be done using software simulations in tools like Logisim.
Selected
I applied via Campus Placement and was interviewed before Jun 2023. There were 2 interview rounds.
(2 Questions)
- Q1. Basics of cmos, working of cmos etc
- Q2. Aptitude questions, logic design questions
(2 Questions)
- Q1. Based on resume, projects done in college
- Q2. CMOS basics, synchronous clocks etc etc
Selected
I applied via LinkedIn and was interviewed in Jun 2022. There were 3 interview rounds.
(1 Question)
- Q1. About your personality and how you think that you will fit for this job?
(1 Question)
- Q1. Why you want to join this company?
Interview Preparation Tips
alex john jacob
Selected
I appeared for an interview before Feb 2023.
(1 Question)
- Q1. PnR flow,Synthesis,STA
I applied via Naukri.com and was interviewed in Jun 2021. There were 5 interview rounds.
Interview Questionnaire
2 Questions
- Q1. Related to projects i have worked on
- Q2. Share exactly what you have worked on.
- Ans.
I have worked on scalable web applications, cloud services, and team leadership in software development projects.
Developed a microservices architecture for an e-commerce platform, improving scalability and maintainability.
Led a team of 5 engineers in building a real-time data processing system using Apache Kafka and Spring Boot.
Implemented CI/CD pipelines using Jenkins and Docker, reducing deployment time by 40%.
Collab...
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I applied via Recruitment Consultant and was interviewed before May 2020. There were 3 interview rounds.
Interview Questionnaire
2 Questions
- Q1. DS and Algo questions based on DP and backtracking
- Q2. Clone linked list with random pointers.
- Ans.
Clone a linked list with random pointers.
Create a new node for each node in the original list.
Store the mapping between the original and cloned nodes in a hash table.
Traverse the original list again and set the random pointers in the cloned list using the hash table.
Return the head of the cloned list.
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